Correlators, by Randy Roberts, RF/SS Consulting

The real "art" or trade secret technology of Spread Spectrum is in the acquisition and tracking of code phase, carrier frequency and data clock. The only "magic" involved is a practical knowledge of how to do it with correlators. Correlators come in various types:
Analog / SAW correlator / SAW convolver / CCD delay line / Doubly balanced mixer
Digital / Full parallel / Sliding / Hybrid / DSP algorithm based / AI "smart" correlator
There are plenty of references on correlators and lots of theoretical analyses of how they are supposed to work. However, in the real world it is best to have a favorite circuit or two that has worked well for you in the past and then adapt or modify it for a new application. I will present a few such circuit ideas here. First, the simplest and quickest correlator to get up and running, by far, is the simple serial, sliding correlator with either two (Tau Dither) or three (Delay Lock/Early-Late) channels, each containing EXOR's or DBM (doubly balanced mixer) correlators. In this approach, one channel is devoted to "on-time" or data channel correlation. In the Tau-Dither two channel system, the second channel is time shared between a slightly "early" and a slightly "late" timing offset channel used to form a "discriminator" function for code tracking purposes. In the three channel system one timing channel is always "early," while the other is always "late." Again a discriminator-like error function is generated to enable code tracking. To better understand the strategy behind the sliding correlator, assume that the receiver has no knowledge at all of the code phase or frequency to be received. The simplest strategy is just to sequentially try each possible code position until correlation is found. The "data" channel mentioned above is used to detect "code lock," since the signal instantly de-spreads and a narrow band carrier (possibly with data modulation) magically appears when code lock is achieved. Sliding correlators are simple, reliable and slow! A hybrid, serial/parallel or "pipelined" approach can speed up this type of correlator by a factor of N2, where N is the number of separate, parallel pipelined channels. Thus a 3-way pipelined hybrid sliding correlator, where each parallel pipelined section examines a different section of the code, can acquire sync about 9 times faster than the simple sequential sliding correlator. This is a great return for a nominal addition of circuitry! Today's PLD (Programmable Logic Device) technology makes it easy to implement hybrid sliding correlators up to near the complexity of a full parallel digital correlator. However, the fastest correlators are fully parallel devices -- they search the entire code epoch length all at once. These devices can use CCDs, SAW (Surface Acoustic Wave) or digital LSI/ASIC technology. SAW convolvers can designed to be programmable for any code -- but the most useful and general purpose parallel correlator is the all-digital device. The chip block diagrams at left and below show some of the available ASIC offerings from Intersil (formerly Harris), TRW and Zilog. Actually Zilog has licensed the SS technology developed by Stanford telecommunications, Inc. for consumer scale commercial development.
The chips shown here are just a sampling of what's available from these and other vendors out there. All three chips shown perform superbly in a correctly interfaced SS system. There is an art to using any of these chips, however. It seems that even to read the data sheets of these chips you need a PhD in microprocessors and silicon BiCMOS technology! Each vendor does make available a certain level of application support -- Stanford Telecom sells evaluation boards and complete development/simulation circuit board subsystems. My recommendation is to select a chip based on the performance you need, build up a simple all-digital test circuit first, then proceed slowly, in small steps, to integrate your new correlator into your SS system. This way you will learn some of the idiosyncrasies of the chip at each step of your design/integration project. Many companies have spent hundreds of thousands or millions of dollars developing their own full parallel digital correlators. Save your company and your project (as well a your reputation) the time, trouble and expense -- use an existing LSI / ASIC parallel digital correlator chip. Parallel correlators can sync up in as little as one code epoch (the code repeat time interval). However, noise and statistics usually enter the picture by forcing certain PFA and PD requirements on you. It is thus typical that all digital parallel correlators synch in perhaps 3 to 5 PN code epochs (data bit times). Even this speed is blazingly fast compared to the sliding correlator which syncs up, at best, in the code length's number of data bits. The use of digital circuitry for correlation provides interesting challenges to the SS innovator -- first it forces him to include both analog and digital circuitry in his design. Next, he must learn something of the rudiments of digital signal processing, if he is to succeed in his efforts. Finally he must learn, by trial of fire and smoke, that SS design is a field for those brave, persevering few who can master multiple technologies and disciplines.