Last month we talked about DS (Direct Sequence) correlaters in general. We covered an introduction to most of the different types of correlators used today. This month we will concentrate a little on the so called Serial Sliding correlator. This type of analog or digital or analog/digital hybrid implementation is the most commonly used correlator today. It is easy to get working. It is easy to design. It is simple to get working and align. Finally, it is a sure-fire, almost idiot-proof way of correlating a locally generated code against the incoming coded signals. Key to making this correlator work is that it must be embedded into a multi-channel PN correlation/detection scheme. One way of doing this is shown below in figure 1. In this design a three channel, "Delay Lock" or "Early- Late" correlator design is used. Three time-staggered samples of the PN code are required to make this design work. The time-staggered code samples are easily generated by driving a two or three bit shift register with your locally generated PN code. The actual time stagger used depends on the priorities of your design. It can be any rational fraction of a "chip" -- up to one full chip. Don't make it more than one full chip, however -- it will rapidly loose correlation gain beyond one full chip because of the triangular nature of the PN autocorrelation function. The actual data demodulation is done in the "center" channel. The DC outputs of the "Early" and "Late" channels are subtracted from each other in an Op Amp. The difference between the Early and Late channel correlations forms a straight line, triangulalar-looking, discriminator "S-curve" of the time difference between the local and incoming codes. This DC signal can be filtered and used to close an AFC type tracking loop around the local PN clock source (VCXO or VCO). Thus this correlator architecture is capable of demodulating the data (the de-spreading correlation operation) and generating a time tracking reference signal for the receiver it's used with.
You need more than just the circuitry shown, however! First the initial frequency of the receive PN clock must be offset, by some small amount, from the transmitting PN clock. This frequency offset causes a beat note between the two signals that actually slowly sweeps the received PN timing across the transmitted signal's PN timing. Thus the name "Sliding Correlator." Normally this frequency offset is easy to achieve, because only by a very fortunate accident would the TX and RX PN clocks be on exactly the "right" frequency, and they probably would not stay on the exact same frequency for long anyway. Next month we'll show you how to control the actual TX and RX frequency offsets precisely, in a fully digital manner. For now, suffice it to say that it is desirable to control the frequency offset between TX and RX PN clock generators! This controlled time offset allows the sliding correlator to sweep precisely through the unknown time delay repetitively so that sync-up time can be controlled. Authors Note: We never did finish this thread -- I guess we just forgot! But, for those curious few, here are some tips about how to "slide" the local code by the incoming code and thus reliably make a sliding correlator work. There are two basic schemes to do this digitally (remember the object here is to shift the reference code in controlled increments AND dwell at that code phase long enough to find signal correlation, if it is present!):
Store all possible phase shifts of the code in microprocessor ROM or an outboard E/EE PROM. Then digitally step through all possible reference code phases, dwelling at each at least ONE data bit time (a PN Epoch), thus looking for correlation.
Use what we call an Incremental Phase Modulator (IPM) -- simply use a clock that is 4 to 16 times the chip rate clock for the system digital timing reference in the receiver. Follow this clock with a programmable frequency divider -- e.g., if the clock is 4 x the PN chip rate, use a divide by 3/4/5 counter. In the case of a clock at 8 x the PN chip rate, use a programmable 7/8/9 counter. Make sure this counter is controlled in such a way that it adds or drops only one input clock each time it is adjusted -- this gives us single PN chip phase adjustment capability! Also make sure that the counter can be advanced or retarded only once per data bit time (or one PN Epoch)! This scheme is especially useful in designs using FPGAs or planning to use custom ASICs, because it lends itself to simple, straightforward digital implementation. Note that, by proper design, ONLY advancing OR retarding of the PN chip phase is necessary -- but be careful of long term PN clock oscillator drifts!
Figure 2, below, shows an alternative implementation of the Delay Lock DS loop. This scheme is useful for a DSP based or- more digital demodulation / correlation implementation. The performance of the two block diagrams is identical if the baseband low pass filters of figure 2 match the equivalent bandpass characteristics of the filters in figure 1.
You need more than just the circuitry shown, however! First the initial frequency of the receive PN clock must be offset, by some small amount, from the transmitting PN clock. This frequency offset causes a beat note between the two signals that actually slowly sweeps the received PN timing across the transmitted signal's PN timing. Thus the name "Sliding Correlator." Normally this frequency offset is easy to achieve, because only by a very fortunate accident would the TX and RX PN clocks be on exactly the "right" frequency, and they probably would not stay on the exact same frequency for long anyway. Next month we'll show you how to control the actual TX and RX frequency offsets precisely, in a fully digital manner. For now, suffice it to say that it is desirable to control the frequency offset between TX and RX PN clock generators! This controlled time offset allows the sliding correlator to sweep precisely through the unknown time delay repetitively so that sync-up time can be controlled. Authors Note: We never did finish this thread -- I guess we just forgot! But, for those curious few, here are some tips about how to "slide" the local code by the incoming code and thus reliably make a sliding correlator work. There are two basic schemes to do this digitally (remember the object here is to shift the reference code in controlled increments AND dwell at that code phase long enough to find signal correlation, if it is present!):
Store all possible phase shifts of the code in microprocessor ROM or an outboard E/EE PROM. Then digitally step through all possible reference code phases, dwelling at each at least ONE data bit time (a PN Epoch), thus looking for correlation.
Use what we call an Incremental Phase Modulator (IPM) -- simply use a clock that is 4 to 16 times the chip rate clock for the system digital timing reference in the receiver. Follow this clock with a programmable frequency divider -- e.g., if the clock is 4 x the PN chip rate, use a divide by 3/4/5 counter. In the case of a clock at 8 x the PN chip rate, use a programmable 7/8/9 counter. Make sure this counter is controlled in such a way that it adds or drops only one input clock each time it is adjusted -- this gives us single PN chip phase adjustment capability! Also make sure that the counter can be advanced or retarded only once per data bit time (or one PN Epoch)! This scheme is especially useful in designs using FPGAs or planning to use custom ASICs, because it lends itself to simple, straightforward digital implementation. Note that, by proper design, ONLY advancing OR retarding of the PN chip phase is necessary -- but be careful of long term PN clock oscillator drifts!
Figure 2, below, shows an alternative implementation of the Delay Lock DS loop. This scheme is useful for a DSP based or- more digital demodulation / correlation implementation. The performance of the two block diagrams is identical if the baseband low pass filters of figure 2 match the equivalent bandpass characteristics of the filters in figure 1.
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