Last month we presented some ideas about delay lock and tau dither circuits for sliding correlators. We also discussed parallel and hybrid digital correlators. This month we will discuss some correlation basics and show some detailed issues that must be addressed when implementing correlators. We also hint at how to build that "nifty" hybrid digital correlator. The basic definition of mathematical correlation is the integral :
Don Lancaster in the August 1992 issue of Electronics Now showed that correlation can be performed in the three different ways, as shown in figures 1 and 2.
One of the problems inherent in the implementation of digital correlator circuitry is that the correlator's ideal triangular shape usually gets digitized as shown in figure 3.
Another real world problem is time sidelobes and poor choices of PN codes. Figure 4 shows what these can look like.
So now you know some of the real world limitations of correlators. You may ask -- how bad are these effects??! You may also ask -- are there other effects that must be accounted for? The answers to these questions are not a simple yes or no. First, you may need to model all the imperfections, quantization errors, noise and code effects before you really know how bad they are. Second, other imperfections can creep into your design. The foremost among these other problems is the effect of bandlimiting on the shape of the correlation triangle. In most cases, some RF or IF bandpass filtering is used in any real world transmitter or receiver. This rounds out the peak of the correlation triangle, loses a little correlation gain and spreads out / rounds out the sharp corners of the correlation function near the baseline. Other problems to watch out for are in-chip multipath signals and intersymbol interference. All this sounds complicated, doesn't it? Well that's part of what keeps us SS consultants busy. It's not really so bad if you use communications block diagram analysis and system modeling tools. TESLA is a PC based tool widely used for- electronic system modeling and optimization. COMDISCO has an expensive, workstation-based package that does everything but wash the dishes. It is a super package, but it costs an arm and a leg! Figure 5 shows how to build an analog "parallel" correlator. You might use a SAW device or a CCD shift register for this scheme. It is essentially an analog perfectly matched filter- for the PN code being transmitted. The output sum can be fed to a threshold circuit (a comparator) to mark the time occurrence of synchronization. Once correlation sync is obtained, the tracking function (delay lock or tau-dither) can be initiated and you are now ready to demodulate the data that follows the unmodulated "sync preamble."
An all-digital, baseband version of the "matched filter" correlation detector is shown in figure 6. This scheme is also implemented at baseband and is a practical scheme that can be used for real world SS communications. Specifically, this correlation should be done on I and Q (quadrature) components of the receiver's IF. This requires sampling the IF signal at a rate equal to, or above, the PN clock.
Don Lancaster in the August 1992 issue of Electronics Now showed that correlation can be performed in the three different ways, as shown in figures 1 and 2.
One of the problems inherent in the implementation of digital correlator circuitry is that the correlator's ideal triangular shape usually gets digitized as shown in figure 3.
Another real world problem is time sidelobes and poor choices of PN codes. Figure 4 shows what these can look like.
So now you know some of the real world limitations of correlators. You may ask -- how bad are these effects??! You may also ask -- are there other effects that must be accounted for? The answers to these questions are not a simple yes or no. First, you may need to model all the imperfections, quantization errors, noise and code effects before you really know how bad they are. Second, other imperfections can creep into your design. The foremost among these other problems is the effect of bandlimiting on the shape of the correlation triangle. In most cases, some RF or IF bandpass filtering is used in any real world transmitter or receiver. This rounds out the peak of the correlation triangle, loses a little correlation gain and spreads out / rounds out the sharp corners of the correlation function near the baseline. Other problems to watch out for are in-chip multipath signals and intersymbol interference. All this sounds complicated, doesn't it? Well that's part of what keeps us SS consultants busy. It's not really so bad if you use communications block diagram analysis and system modeling tools. TESLA is a PC based tool widely used for- electronic system modeling and optimization. COMDISCO has an expensive, workstation-based package that does everything but wash the dishes. It is a super package, but it costs an arm and a leg! Figure 5 shows how to build an analog "parallel" correlator. You might use a SAW device or a CCD shift register for this scheme. It is essentially an analog perfectly matched filter- for the PN code being transmitted. The output sum can be fed to a threshold circuit (a comparator) to mark the time occurrence of synchronization. Once correlation sync is obtained, the tracking function (delay lock or tau-dither) can be initiated and you are now ready to demodulate the data that follows the unmodulated "sync preamble."
An all-digital, baseband version of the "matched filter" correlation detector is shown in figure 6. This scheme is also implemented at baseband and is a practical scheme that can be used for real world SS communications. Specifically, this correlation should be done on I and Q (quadrature) components of the receiver's IF. This requires sampling the IF signal at a rate equal to, or above, the PN clock.
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